Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:13.4 (WebPack) - O.87xd Target Family: Spartan3A and Spartan3AN
OS Platform: NT64 Target Device: xc3s400a
Project ID (random number) 9d99e58cd3f9466faf5c88eb5c23f77e.178B53D7622C46729C4E6F226DD39E51.1 Target Package: ft256
Registration ID 174792475_203016486_208889959_663 Target Speed: -4
Date Generated 2012-07-04T11:24:10 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i5-2520M CPU @ 2.50GHz CPU Speed 2491 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=1
  • 4-bit adder=1
Counters=8
  • 20-bit up counter=1
  • 24-bit up counter=1
  • 5-bit up counter=4
  • 5-bit updown counter=2
FSMs=2 RAMs=2
  • 32x8-bit dual-port distributed RAM=2
Registers=131
  • Flip-Flops=131
MiscellaneousStatistics
  • AGG_BONDED_IO=69
  • AGG_IO=69
  • AGG_SLICE=203
  • NUM_4_INPUT_LUT=300
  • NUM_BONDED_IBUF=31
  • NUM_BONDED_IOB=38
  • NUM_BUFGMUX=2
  • NUM_CYMUX=47
  • NUM_DCM=1
  • NUM_DP_RAM=64
  • NUM_LUT_RT=42
  • NUM_ODDR2_NONE=1
  • NUM_SHIFT=2
  • NUM_SLICEL=169
  • NUM_SLICEM=34
  • NUM_SLICE_FF=247
  • NUM_XOR=44
NetStatistics
  • NumNets_Active=481
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=187
  • NumNodesOfType_Active_CNTRLPIN=231
  • NumNodesOfType_Active_DOUBLE=796
  • NumNodesOfType_Active_DUMMY=927
  • NumNodesOfType_Active_DUMMYBANK=3
  • NumNodesOfType_Active_DUMMYESC=41
  • NumNodesOfType_Active_GLOBAL=88
  • NumNodesOfType_Active_HFULLHEX=19
  • NumNodesOfType_Active_HLONG=3
  • NumNodesOfType_Active_HUNIHEX=51
  • NumNodesOfType_Active_INPUT=1127
  • NumNodesOfType_Active_IOBOUTPUT=39
  • NumNodesOfType_Active_OMUX=430
  • NumNodesOfType_Active_OUTPUT=373
  • NumNodesOfType_Active_PREBXBY=396
  • NumNodesOfType_Active_VFULLHEX=93
  • NumNodesOfType_Active_VLONG=29
  • NumNodesOfType_Active_VUNIHEX=87
  • NumNodesOfType_Gnd_CLKPIN=1
  • NumNodesOfType_Gnd_CNTRLPIN=2
  • NumNodesOfType_Gnd_DOUBLE=8
  • NumNodesOfType_Gnd_DUMMYBANK=3
  • NumNodesOfType_Gnd_INPUT=6
  • NumNodesOfType_Gnd_OMUX=6
  • NumNodesOfType_Gnd_OUTPUT=6
  • NumNodesOfType_Gnd_PREBXBY=6
SiteStatistics
  • IBUF-DIFFMI_NDT=1
  • IBUF-DIFFMLR=5
  • IBUF-DIFFMTB=10
  • IBUF-DIFFSI_NDT=1
  • IBUF-DIFFSLR=5
  • IBUF-DIFFSTB=8
  • IOB-DIFFMLR=5
  • IOB-DIFFMTB=14
  • IOB-DIFFSLR=5
  • IOB-DIFFSTB=14
  • SLICEL-SLICEM=64
SiteSummary
  • BUFGMUX=2
  • BUFGMUX_GCLKMUX=2
  • BUFGMUX_GCLK_BUFFER=2
  • DCM=1
  • DCM_DCM=1
  • IBUF=31
  • IBUF_DELAY_ADJ_BBOX=31
  • IBUF_INBUF=31
  • IBUF_PAD=31
  • IOB=38
  • IOB_DELAY_ADJ_BBOX=8
  • IOB_INBUF=8
  • IOB_OFF1=1
  • IOB_OFF2=1
  • IOB_OFFDDRBLACKBOX=1
  • IOB_OUTBUF=38
  • IOB_PAD=38
  • SLICEL=169
  • SLICEL_C1VDD=5
  • SLICEL_C2VDD=2
  • SLICEL_CYMUXF=25
  • SLICEL_CYMUXG=22
  • SLICEL_F=116
  • SLICEL_F5MUX=21
  • SLICEL_FFX=133
  • SLICEL_FFY=114
  • SLICEL_G=118
  • SLICEL_GNDF=20
  • SLICEL_GNDG=20
  • SLICEL_XORF=22
  • SLICEL_XORG=22
  • SLICEM=34
  • SLICEM_F=32
  • SLICEM_G=34
  • SLICEM_WSGEN=34
 
Configuration Data
BUFGMUX
  • S=[S_INV:2] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:2]
  • S=[S_INV:2] [S:0]
DCM
  • PSCLK=[PSCLK_INV:0] [PSCLK:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:0]
  • RST=[RST:1] [RST_INV:0]
DCM_DCM
  • CLKDV_DIVIDE=[8:1]
  • CLKOUT_PHASE_SHIFT=[NONE:1]
  • CLK_FEEDBACK=[1X:1]
  • DESKEW_ADJUST=[9:1]
  • DFS_FREQUENCY_MODE=[LOW:1]
  • DLL_FREQUENCY_MODE=[LOW:1]
  • DUTY_CYCLE_CORRECTION=[TRUE:1]
  • FACTORY_JF1=[0XC0:1]
  • FACTORY_JF2=[0X80:1]
  • PSCLK=[PSCLK_INV:0] [PSCLK:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:0]
  • RST=[RST:1] [RST_INV:0]
IBUF_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:31]
  • IBUF_DELAY_VALUE=[DLY0:31]
  • IFD_DELAY_VALUE=[DLY0:31]
  • SEL_IN=[SEL_IN:31] [SEL_IN_INV:0]
IBUF_PAD
  • IOATTRBOX=[LVCMOS33:31]
IOB
  • O1=[O1_INV:7] [O1:31]
  • O2=[O2:1] [O2_INV:0]
  • OCE=[OCE:1] [OCE_INV:0]
  • OTCLK1=[OTCLK1_INV:0] [OTCLK1:1]
  • OTCLK2=[OTCLK2_INV:1] [OTCLK2:0]
  • T1=[T1_INV:0] [T1:8]
IOB_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:8]
  • IBUF_DELAY_VALUE=[DLY0:8]
  • IFD_DELAY_VALUE=[DLY0:8]
  • SEL_IN=[SEL_IN:8] [SEL_IN_INV:0]
IOB_OFF1
  • CE=[CE:1] [CE_INV:0]
  • CK=[CK:1] [CK_INV:0]
  • D=[D:1] [D_INV:0]
  • LATCH_OR_FF=[FF:1]
  • OFF1_INIT_ATTR=[INIT0:1]
IOB_OFF2
  • CE=[CE:1] [CE_INV:0]
  • CK=[CK:0] [CK_INV:1]
  • D=[D:1] [D_INV:0]
  • LATCH_OR_FF=[FF:1]
  • OFF2_INIT_ATTR=[INIT0:1]
IOB_OUTBUF
  • IN=[IN_INV:7] [IN:31]
  • SUSPEND=[3STATE:38]
  • TRI=[TRI_INV:0] [TRI:8]
IOB_PAD
  • DRIVEATTRBOX=[2:38]
  • IOATTRBOX=[LVCMOS33:38]
  • SLEW=[SLOW:38]
SLICEL
  • BX=[BX_INV:6] [BX:65]
  • BY=[BY:47] [BY_INV:0]
  • CE=[CE:67] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:22]
  • CLK=[CLK:149] [CLK_INV:0]
  • SR=[SR:123] [SR_INV:0]
SLICEL_CYMUXF
  • 0=[0:25] [0_INV:0]
  • 1=[1_INV:0] [1:25]
SLICEL_CYMUXG
  • 0=[0:22] [0_INV:0]
SLICEL_F5MUX
  • S0=[S0:21] [S0_INV:0]
SLICEL_FFX
  • CE=[CE:66] [CE_INV:0]
  • CK=[CK:133] [CK_INV:0]
  • D=[D:127] [D_INV:6]
  • FFX_INIT_ATTR=[INIT0:127] [INIT1:6]
  • FFX_SR_ATTR=[SRLOW:127] [SRHIGH:6]
  • LATCH_OR_FF=[FF:133]
  • SR=[SR:109] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:133]
SLICEL_FFY
  • CE=[CE:57] [CE_INV:0]
  • CK=[CK:114] [CK_INV:0]
  • D=[D:114] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:102] [INIT1:12]
  • FFY_SR_ATTR=[SRLOW:102] [SRHIGH:12]
  • LATCH_OR_FF=[FF:114]
  • SR=[SR:88] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:114]
SLICEL_XORF
  • 1=[1_INV:0] [1:22]
SLICEM
  • BY=[BY:34] [BY_INV:0]
  • CLK=[CLK:34] [CLK_INV:0]
  • SR=[SR:34] [SR_INV:0]
SLICEM_F
  • DI=[DI:32] [DI_INV:0]
  • F_ATTR=[DUAL_PORT:32]
  • LUT_OR_MEM=[RAM:32]
SLICEM_G
  • DI=[DI:34] [DI_INV:0]
  • G_ATTR=[DUAL_PORT:32] [SHIFT_REG:2]
  • LUT_OR_MEM=[RAM:34]
SLICEM_WSGEN
  • CK=[CK:34] [CK_INV:0]
  • WE=[WE_INV:0] [WE:34]
 
Pin Data
BUFGMUX
  • I0=2
  • O=2
  • S=2
BUFGMUX_GCLKMUX
  • I0=2
  • OUT=2
  • S=2
BUFGMUX_GCLK_BUFFER
  • IN=2
  • OUT=2
DCM
  • CLK0=1
  • CLKDV=1
  • CLKFB=1
  • CLKIN=1
  • LOCKED=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
DCM_DCM
  • CLK0=1
  • CLKDV=1
  • CLKFB=1
  • CLKIN=1
  • LOCKED=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
IBUF
  • I=31
  • PAD=31
IBUF_DELAY_ADJ_BBOX
  • IBUF_OUT=31
  • SEL_IN=31
IBUF_INBUF
  • IN=31
  • OUT=31
IBUF_PAD
  • PAD=31
IOB
  • I=8
  • O1=38
  • O2=1
  • OCE=1
  • OTCLK1=1
  • OTCLK2=1
  • PAD=38
  • T1=8
IOB_DELAY_ADJ_BBOX
  • IBUF_OUT=8
  • SEL_IN=8
IOB_INBUF
  • IN=8
  • OUT=8
IOB_OFF1
  • CE=1
  • CK=1
  • D=1
  • Q=1
IOB_OFF2
  • CE=1
  • CK=1
  • D=1
  • Q=1
IOB_OFFDDRBLACKBOX
  • OFF1=1
  • OFF2=1
  • OFFDDR=1
IOB_OUTBUF
  • IN=38
  • OUT=38
  • TRI=8
IOB_PAD
  • PAD=38
SLICEL
  • BX=71
  • BY=47
  • CE=67
  • CIN=22
  • CLK=149
  • COUT=22
  • F1=112
  • F2=90
  • F3=78
  • F4=45
  • G1=118
  • G2=96
  • G3=83
  • G4=41
  • SR=123
  • X=32
  • XB=1
  • XQ=133
  • Y=32
  • YQ=114
SLICEL_C1VDD
  • 1=5
SLICEL_C2VDD
  • 1=2
SLICEL_CYMUXF
  • 0=25
  • 1=25
  • OUT=25
  • S0=25
SLICEL_CYMUXG
  • 0=22
  • 1=22
  • OUT=22
  • S0=22
SLICEL_F
  • A1=112
  • A2=90
  • A3=78
  • A4=45
  • D=116
SLICEL_F5MUX
  • F=21
  • G=21
  • OUT=21
  • S0=21
SLICEL_FFX
  • CE=66
  • CK=133
  • D=133
  • Q=133
  • SR=109
SLICEL_FFY
  • CE=57
  • CK=114
  • D=114
  • Q=114
  • SR=88
SLICEL_G
  • A1=118
  • A2=96
  • A3=83
  • A4=41
  • D=118
SLICEL_GNDF
  • 0=20
SLICEL_GNDG
  • 0=20
SLICEL_XORF
  • 0=22
  • 1=22
  • O=22
SLICEL_XORG
  • 0=22
  • 1=22
  • O=22
SLICEM
  • BY=34
  • CLK=34
  • F1=32
  • F2=32
  • F3=32
  • F4=32
  • G1=34
  • G2=34
  • G3=34
  • G4=34
  • SR=34
  • X=32
  • Y=2
SLICEM_F
  • A1=32
  • A2=32
  • A3=32
  • A4=32
  • D=32
  • DI=32
  • WF1=32
  • WF2=32
  • WF3=32
  • WF4=32
  • WS=32
SLICEM_G
  • A1=34
  • A2=34
  • A3=34
  • A4=34
  • D=2
  • DI=34
  • WG1=32
  • WG2=32
  • WG3=32
  • WG4=32
  • WS=34
SLICEM_WSGEN
  • CK=34
  • WE=34
  • WSF=32
  • WSG=34
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400a-ft256-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400a-ft256-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 20 13 0 0 0 0 0
bitgen 10 10 0 0 0 0 0
map 12 11 0 0 0 0 0
ngdbuild 14 14 0 0 0 0 0
par 11 11 0 0 0 0 0
trce 11 11 0 0 0 0 0
xst 27 26 0 0 0 0 0
 
Project Statistics
PROP_Board= PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_PropSpecInProjFile=Store all values PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2012-07-04T11:23:09 PROP_intWbtProjectID=178B53D7622C46729C4E6F226DD39E51
PROP_intWbtProjectIteration=1 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_AutoTop=true
PROP_DevFamily=Spartan3A and Spartan3AN PROP_DevDevice=xc3s400a
PROP_DevFamilyPMName=spartan3a PROP_DevPackage=ft256
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-4
PROP_PreferredLanguage=Verilog FILE_UCF=1
FILE_VERILOG=4
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_DCM_SP=1 NGDBUILD_NUM_FD=26 NGDBUILD_NUM_FDC=81
NGDBUILD_NUM_FDCE=98 NGDBUILD_NUM_FDE=24 NGDBUILD_NUM_FDP=17 NGDBUILD_NUM_FDPE=1
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=30 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=15
NGDBUILD_NUM_IOBUF=8 NGDBUILD_NUM_LUT1=42 NGDBUILD_NUM_LUT2=25 NGDBUILD_NUM_LUT3=75
NGDBUILD_NUM_LUT4=86 NGDBUILD_NUM_MUXCY=47 NGDBUILD_NUM_MUXF5=21 NGDBUILD_NUM_OBUF=30
NGDBUILD_NUM_ODDR2=1 NGDBUILD_NUM_RAM16X1D=32 NGDBUILD_NUM_SRL16=2 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=44
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_DCM_SP=1 NGDBUILD_NUM_FD=26 NGDBUILD_NUM_FDC=81
NGDBUILD_NUM_FDCE=98 NGDBUILD_NUM_FDE=24 NGDBUILD_NUM_FDP=17 NGDBUILD_NUM_FDPE=1
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=38 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=15
NGDBUILD_NUM_LUT1=42 NGDBUILD_NUM_LUT2=25 NGDBUILD_NUM_LUT3=75 NGDBUILD_NUM_LUT4=86
NGDBUILD_NUM_MUXCY=47 NGDBUILD_NUM_MUXF5=21 NGDBUILD_NUM_OBUF=30 NGDBUILD_NUM_OBUFT=8
NGDBUILD_NUM_ODDR2=1 NGDBUILD_NUM_SRLC16E=2 NGDBUILD_NUM_TS_TIMESPEC=1 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=44
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s400a-4-ft256 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=500 -bufg=24
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5